The present invention relates to methods and structures for the fabrication of multilevel interconnects in integrated circuits, and more particularly to hardmask structure and processes for dual damascene integration.
An integrated circuit device contains transistors connected by multiple levels of metal interconnects. These metal interconnects (lines or plugs) are separated from each other by interlayer dielectrics (ILD)xe2x80x94i.e. the electrically insulating material between metal interconnects. The metal interconnects are found in lines or trenches that within a layer are separated from each other by the ILD. This layer is sometimes referred to as the trench layer. In addition, metal lines in adjacent trench layers are separated by via layers that contain holes or vias filled with conducting metal also in ILD material. This layer is sometimes referred to as the via layer.
Conventionally, integrated circuit articles have been made using SIOx as the interlayer dielectric (ILD). However, as integrated circuit device features have become smaller the dielectric properties of SiOx were recognized to be insufficient to prevent cross-talk and other interference causing decreased circuit performance. Thus, alternative materials xe2x80x9clow-kxe2x80x9d materials having lower dielectric constants (less than 3.0) are being developed. These low dielectric constant materials fall within two compositional categories: those that contain significant amounts of silicon forming the backbone of the molecular structure (referred to herein as inorganic dielectrics) and those composed primarily of carbon forming the backbone of the molecular structure (referred to herein as organic dielectrics). While inorganic dielectrics are formed primarily with silicon and, optionally oxygen, in the backbone, these inorganic dielectrics may contain organic portions. Similarly, while the organic dielectrics contain primarily carbon, and optionally oxygen, in the backbone, they may also have a small amount of silicon or other like molecules in the composition. According to the above definition, examples of inorganic low dielectric constant materials are silsesquioxanes, and the like. According to the above definition, examples of organic low dielectric constant materials, are polyarylenes, including polyarylene ethers (e.g. SiLK(trademark) dielectric resins from The Dow Chemical Company, Flare(trademark) resins from Honeywell) and benzocyclobutene based resins (e.g. Cyclotene(trademark) resins from The Dow Chemical Company which include some Si atoms in their structure). Moreover, as the feature sizes are being pushed even smaller in integrated circuits, porous dielectric layers are being used to further reduce the dielectric constant and improve electrical insulative properties.
In addition to material selection, method of manufacture (referred to as integration) of the integrated circuit article is also of vital importance. In one common method of manufacture known as dual damascene, the via and trench layer dielectric material or materials are applied, vias and trenches are formed in these layers by removing the dielectric material to form the desired via and trench pattern, and the via and trench are filled with the conducting metal. The formation of the vias and trenches can be quite complex using a variety of lithographic techniques that include photoresists, mask layers, various etch processes, etc.
One common dual damascene approach uses an etch stop layer between the via layer dielectric which is applied first to the substrate and the trench layer dielectric to form a trilayer dielectric stack. See e.g. U.S. Pat. No. 6,071,809 where an inorganic dielectric layer is used between two low-k organic dielectric layers. In WO01/18861, Chung et al., recognized that by selecting the middle dielectric layer to be of a different class (i.e. organic or inorganic class) from the via and trench level dielectric material, all the materials in the stack may be low-k dielectrics, thus, lowering the overall effective dielectric constant of the trilayer stack. Chung particularly focuses on a trilayer dielectric stack that has two inorganic layers separated by an organic layer and teaches use of organic photoresists over the top inorganic layer to form the patterns in the dielectric stack.
A complication that arises when organic dielectrics are used is that the etch rates for photoresist and organic dielectrics are very similar. This makes forming the vias and trenches in such organic dielectrics more complex. In addition, the ability of the top portion of the dielectric stack to withstand chemical mechanical polishing (CMP) may become difficult if that portion is an organic dielectric. Thus, in the case where the contact and trench dielectric materials are organic, two inorganic hardmasks are conventionally deposited by chemical vapor deposition (CVD) on top of the tri-layer dielectric to facilitate the patterning process. For example, Zhao, in U.S. Pat. No. 6,071,809, discloses a method for forming dual damascene structures in a tri-layer dielectric by the use of a dual hardmask composed of CVD silicon oxide and CVD silicon nitride. When the contact and trench dielectrics are applied by spin coating as is most common for organic dielectrics, the addition of CVD processes in the masking construction is complex, expensive, and limits throughput.
xe2x80x9cA High Performance 0.13 mm Copper BEOL Technology with Low-k Dielectric,xe2x80x9d R. D. Goldblatt et. al., Proc. IITC, June 2000, page 261-263, describes a dual damascene approach for patterning in a monolithic dielectric material in which both the via and trench will be formed. This method requires rigorous control of the plasma etch conditions so as to maintain a planar surface as the etch-front advances into the layer being etched. Presuming, the ability to maintain this etch morphology, the monolithic dielectric is capable of both reducing the process complexity by the elimination of the etch stop while reducing the overall capacitance in the dielectric construction.
Spin on etch stops and hardmasks have been taught (see e.g. U.S. Pat. No. 6,265,319 and U.S. Pat. No. 6,218,078) in simple single layer masking systems.
Applicants have invented a simple, convenient mask system and dual damascene patterning method for monolithic or tri-layer dielectric stacks that would provide the necessary etch selectivity while taking into account the desire to use a single deposition method (e.g. spin coating) for applying the dielectric material and the masking material and the use of dielectric materials that may be susceptible to damage during CMP steps (e.g. organic dielectrics and porous dielectrics). This system has the additional benefit that, if desired, it can be used to minimize the number of distinct raw materials that are used in making the metal interconnect structure in the microelectronic device.
Thus, according to a first embodiment, the invention is an article comprising
a) a substrate,
b) on the substrate, a dielectric stack comprising a top portion having a dielectric constant of less than 3.0,
c) a first mask layer over the dielectric stack which first mask layer is resistant to erosion by chemical mechanical polishing system which is designed to remove copper and which first layer has etch selectivity relative to the top portion of the dielectric stack,
d) a second mask layer over the first mask layer, which second mask layer has etch selectivity relative to the first mask layer and has etch characteristics similar to those of the top portion of the dielectric stack, and
e) a third mask layer over the second mask layer, which third mask layer has etch selectivity relative to the second mask layer and has etch characteristics similar to those of the first mask layer.
According to a second embodiment, this invention is a method of forming trenches and vias in a dielectric stack comprising the steps of
(a) providing a substrate;
(b) applying the dielectric stack to the substrate wherein the dielectric stack comprises a top portion in which trenches will be formed and a bottom portion in which vias will be formed and an etch stop layer between the top and bottom portions wherein the dielectric constant of each of the top portion and the bottom portion is less than 3.0, preferably less than 2.7;
(c) applying a first mask layer which acts as a stop during the polishing step and which has etch selectivity relative to the top portion of the dielectric stack and has etch characteristics similar to those of the etch stop layer;
(d) applying a second mask layer which has etch selectivity relative to the first mask layer and has etch characteristics similar to those of the top portion of the dielectric stack;
(e) applying a third mask layer which has etch selectivity relative to the second mask layer and having etch characteristics similar to those for the first layer,
(f) patterning the first, second and third mask layers in accordance with a trench pattern
(g) patterning the etch stop layer with a via pattern
(h) etching the trench pattern into the top portion of the dielectric stack to form at least one trench and the via pattern into the bottom portion of the dielectric stack to form at least one via,
(i) depositing a metal in the vias and trenches,
(j) polishing away excess metal wherein the first mask layer serves as a polishing stop,
wherein at least a substantial portion of the third mask layer is removed during patterning of either the first mask layer or the etch stop layer and wherein at least a substantial portion of the second mask layer is removed during etching of the dielectric stack.
According to a third embodiment a method of forming trenches and vias in a dielectric comprising the steps of
(a) providing a substrate;
(b) applying the dielectric layer to the substrate wherein the dielectric layer comprises a top portion in which trenches will be formed and a bottom portion in which vias will be formed and wherein the dielectric constant of the layer is less than 3.0, preferably less than 2.7;
(c) applying a first mask layer which acts as a stop during the polishing step and which has etch selectivity relative to the dielectric layer;
(d) applying a second mask layer which has etch selectivity relative to the first mask layer;
(e) applying a third mask layer which has etch selectivity relative to the second mask layer and which has etch characteristics similar to those of the first mask layer,
(f) patterning the second and third mask layers in accordance with a trench pattern
(g) patterning the first mask layer in accordance with a via pattern,
(h) etching the via pattern a portion of the way into the dielectric layer,
(i) patterning the first mask layer in accordance with the trench pattern made in the second and third mask layers and simultaneously removing a substantial portion of the third mask layer,
(j) continue the etch of the dielectric layer thereby forming at least one via in the bottom portion of the dielectric layer and forming at least one trench in the top portion of the dielectric layer,
(k) wherein the third mask layer is substantially removed during patterning of either the first mask layer or the etch stop layer and wherein the second mask layer is substantially removed during etching of the dielectric stack
(l) depositing a metal in the vias and trenches,
(m) polishing away excess metal wherein the first mask layer serves as a polishing stop.
xe2x80x9cEtch characteristics similar toxe2x80x9d as used herein means that the two materials are etched by the same chemistry with etch selectivity that is in the same range relative to the other materials in the stack. Preferably, these materials will have an etch selectivity ratio relative to one another of less than 5:1, preferably less than 3:1, more preferably less than 2:1.
xe2x80x9cEtch selectivityxe2x80x9d as used herein means that the first and second materials will etch at sufficiently different rates when subjected to an etch chemistry such that each can be patterned separately. Preferably, when layers are stated herein to have etch selectivity relative to another material the layers have etch selectivity ratios of greater than 5:1, more preferably greater than about 7:1 and most preferably greater than about 10:1.
xe2x80x9cEtch selectivity ratioxe2x80x9d as used herein means that for an etch chemistry, the rate at which one material is etched divided by the rate at which a second material is etched.